Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, Power Characterization. Lead technical campaigns and strategies in the Frontend digital implementation space. Aggressively push Power, Performance, and Area (PPA)Deliver technical presentations and lead discussions internally and with customers. Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requiremen... more details
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, Power Characterization.
Lead technical campaigns and strategies in the Frontend digital implementation space.
Aggressively push Power, Performance, and Area (PPA)
Deliver technical presentations and lead discussions internally and with customers.
Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.
Support execution on critical customer flagship product tape outs.
Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
Job Requirements
Minimum
MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 8+ years industry experience.
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.
Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking, Low Power, Power characterization.
Expert in RTL Synthesis and ability to rewrite RTL to accomplish improved PPA.
Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.
Experience with advanced technology nodes including Sub 5nm and below.
Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skillsets.
Strong verbal, written, and customer communication skills.
Preferred
Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.
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The annual salary range for California is $120,400 to $223,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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