Job Abstract

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

As a Physical Design Power Integrity Engineer, you will define on-die power grid methodology and provide solutions to meet Performance, Power and Area (PPA) and IR/EM targets in our mobile designs. In this role, you will collaborate with physical implementation teams to optimize Power Delivery Networks (PDN).

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Define power grid design methodology.
  
• Provide power grid solutions for different design contents (CPU, GPU, SoC, etc.) to achieve optimal Performance, Power, Area (PPA) goals.
  
• Optimize power grids to meet IR/EM requirements.
  
• Guide physical implementation designers on PDN tuning and issue fixing.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, related field, or equivalent practical experience.
  
• 8 years of experience with on-die power grid design for ASIC/SOC.
  
• Experience with IR/EM EDA tools, such as Redhawk and Voltus.
  
• Experience with scripting languages such TCL, Python, or Shell.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or a related field.
  
• Experience in PnR tools and familiarity with digital design PnR flows.
  
• Knowledge of SPICE simulations.