Job Abstract

Who we are: At Synopsys, we’re at the heart of the innovations ushering the Era of Smart Everything, ranging from self-driving cars, Artificial Intelligence, Cloud, 5G and IoT. Chip design today is more complex than ever as it needs to accurately model silicon behavior at vanishingly small geometries while handling large designs with hundreds of millions of logic gates. All while solving a series of NP-hard problems to deliver best in class clock frequencies within tight power budgets. There is a huge opportunity to innovate by developing smarter algorithms, data structures, and machine learning techniques, as we scale our industry leading digital implementation solution for the next generation of powerful chip. If you share our passion for innovation, we want to meet you.

Who You Are: A proactive, results-driven individual with excellent communication skills. You're a team player who thrives in collaborative environments, and you're always seeking innovative solutions to complex problems.

This is what you will be doing:

• Physical design of high performance, energy efficient processors and processor-based sub-systems with very aggressive power and performance targets for a variety of end-user applications
• Development of advanced EDA tools and design methodologies to support these processor implementations.
• Close working collaboration with key Synopsys customers in their development of processor-based platforms in advanced silicon technologies using Synopsys tools and methodologies.
• Work closely with Synopsys R&D and marketing teams to help influence product definition.
• Collaboration with our key IP partners to ensure that the EDA tools, methodology and IP interact seamlessly to enable customers deliver differentiated products in a timely manner.
• Active participation in account strategy & review meetings, conducting hands-on competitive benchmarks as well as research and development of innovative solutions to the complex challenges of delivering power sensitive implementation of high-performance process sub-systems.

This is what you will need:

• BS or MS with 8+ years of applicable experience
• Design experience should include ASIC design using industry-standard tools (PnR, sign off, etc.)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required

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The base salary range across the U.S. for this role is between $152,000 - $ 228,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.